1. Field of the Invention
The present invention relates to a test circuit of a logic LSIs to improve efficiency of testing the logic circuit inside. The test facilitating circuit is generally applicable to data path circuit in an LSI having bus structure such as an arithmetic circuit.
2. Description of the Prior Art
To test a logic circuit, particularly a combinational circuit of large scale integrated (LSI) circuit, a scan pass method and an ad hoc method are widely known to be effective.
According to the scan path method, flip-flops in a logic circuit are used as a shift register to form a scan path. The flip-flops are directly controlled from the outside to test the logic circuit, and then a result of the test is observed by the flip-flops. Namely, sequential circuits including flip-flops are rearranged as a combinational circuit by modifying flip-flops to shift register which is directly controllable and observable according to the scan path method to achieve the test. The scan path method is reliable and effective if testing time and additional hardware are allowed to increase considerably. However, the scan path method is frequently employed to test LSI logic circuits.
The conventional scan path method will be explained with reference to FIG. 1. In the figure, an arithmetic circuit comprises an adder AD, input registers A and B, a data register D, an output inverting device I, an internal data bus B, an output driver BL, and a decoding logic circuit L.sub.1. The decoding logic circuit L.sub.1 generates signals for controlling the circuit elements by decoding the bit pattern of a flip-flop group FF. The registers A and B, data register D and flip-flop group FF are employed to form a scan path according to the scan path method.
The circuit shown in FIG. 1 is a typical example of arithmetic circuit of a microprocessor having bus structure. In the circuit of FIG. 1, two different signal path exist. They are, control signals C.sub.1 to C.sub.6 and a 32-bit data path in which calculation data is transmitted. Therefore, it is necessary to utilize this characteristic in designing a testing circuit.
According to the scan path method, the flip-flops in the flip-flop group FF are simply connected in series to form a shift register that handles both data and control signals in the test. This is not efficient.
Therefore, the scan path method greatly increases testing time due to data transfer in testing a large scale logic circuit block including various arithmetic circuits because it contains 32 bit registers in the shift register. In addition, complexity of a system increases, the number of bits to be involved in a scan path drastically increases to deteriorate testing efficiency.
Meanwhile, the ad hoc method (not particularly shown but FIG. 1 may be referred to as a reference) inserts gates at nodes which are hard to control and observe from the outside of the LSI, for example, nodes 10 of the control lines between the decoding logic L.sub.1 and the adder AD of FIG. 1. The nodes 1 are directly controlled via external pins to carry out a test.
The ad hoc method requires gates to be inserted in the same number as the number of nodes of control lines (six in FIG. 1) to form test points. Moreover, external pins for the exclusive use of test shall be prepared in the same number as the number of the gates. As a result, costs are drastically increased if the number of arithmetic circuits to be tested is increased.